Session 17-2

A 75GHz PLL Front-End Integration in 65nm SOI
CMOS Technology

 

Abstract

A 75GHz PLL front-end, composed of complementary LC VCO, a buffer with AC coupling, and a static CML latch divider, is integrated in 65nm SOI CMOS technology. The circuitry is developed with milli-meter wave link specifications, technology consideration, process variation, and topology selections. The PLL front-end achieves 5.9% tuning range centered at 73.4GHz and free-running phase noise of -110dBc/Hz at 10MHz offset with 71mW.