Session 18-1

A 1.5V, 1.6Gb/s/pin, 1Gb DDR3 SDRAM with an Address Queuing
Scheme and Bang-Bang Jitter Reduced DLL Scheme

 

Abstract

A 1.6Gb/s/pin 1Gb DDR3 SDRAM with a CAS latency of 8 at 1.5V is developed using an 80nm dual poly CMOS process, which consumes 30mA of IDD2N and 160mA of IDD4R. With an address queuing scheme and a self-timed IOSA, IDD4R current can be reduced by 18mA. To achieve 1.6Gb/s/pin operation, a bang-bang jitter free DLL with a split phase interpolator is employed.