Session 18-2

Processor-Based Built-in Self-Optimizer for 90nm
Diode-Switch PRAM

 

Abstract

A PRAM includes 8b embedded RISC to generate the optimized internal timing and voltage parameters to control the variations of the cell resistances. The PRAM blocks with small margin window of cell resistances are detected, analyzed and controlled by processor-based built-in self-optimizer (BISO). A 4Mb test PRAM is fabricated in a 90nm 3-metal diode-switch PRAM cell technology. Measured margin increases by up to 221%.