Session 18-3

Time Discrete Voltage Sensing and Iterative Programming
Control for a 4F2 Multilevel CBRAM

 

Abstract

Multilevel read/write circuits developed for a 90nm, 4F2, 1T1CBJ (1-Transistor/1-Conductive Bridging Junction) 4Mb CBRAM core are described for the first time. The design uses an on-pitch time-discrete voltage sensing scheme and employs a bitline (BL) charge balancing reference as well as a self-timed iterative program concept. Random read cycle times about 0.7us and random write cycle times about 1.35us are achieved.