Session 19-1

A 2.5mW 80dB DR 36dB SNDR 22MS/s Logarithmic Pipeline ADC

 

Abstract

A switched-capacitor logarithmic pipeline ADC scheme that does not require squaring or any other complex analog functions is described. This approach is ideal where high dynamic range, but not high peak SNDR, is required. A signed, 8bit logarithmic pipeline ADC is implemented in 0.18um CMOS. The 22MS/s ADC achieves measured DR of 80dB and measured SNDR of 36dB, occupies 0.56mm2, and consumes 2.54mW from 1.62V supply. The measured dynamic range figure of merit is 174dB.