Session 19-2

A 14b Low-power Pipeline A/D Converter Using a
Pre-charging Technique

 

Abstract

A pre-charging technique to improve the settling response of pipeline stages is demonstrated in a 14bit pipeline A/D converter (ADC). The prototype ADC fabricated in a 0.25um CMOS process consumes 102mW at 30MSample/s. Measured SNDR and SFDR are 70.7dB and 82.8dB, respectively.