Session 2-3

A 19-mode 8.29mm² 52-mW LDPC Decoder Chip
for IEEE 802.16e System

 

Abstract

This paper presents a LDPC decoder chip supporting all 19 modes in IEEE 802.16e system. An efficient design strategy is proposed to reduce 31.25% decoding latency, and enhance hardware utilization ratio from 50% to 75%. Besides, we propose an early termination scheme that can dynamically adjust the number of iterations. The multi-mode chip can be maximally measured at 83.3MHz with only 52mW power consumption. The core area is 4.45mm2 and the die area is 8.29mm2.