Session 21-1

Homogenous Dual-Processor Core with Shared L1
Cache for Mobile Multimedia SoC

 

Abstract

A novel dual-processor core which adopts a shared L1 cache with active way scheme is proposed. In this scheme, each WAY of cache is owned by specific processor. This architecture can realize simultaneous access from both processors with no dual port DATA memory and can guarantee no cache thrashing and no snoop overhead. By adopting this architecture, power is 23% smaller and area is 29 % smaller than dual processor core with snoop cache.