Session 22-4

A Dual PFD Phase Rotating Multi-Phase PLL for 5Gbps
PCI Express Gen2 Multi-Lane Serial Link Receiver in
0.13um CMOS

 

Abstract

A dual phase frequency detector PLL architecture for multi-lane 5Gbps serial link receiver is demonstrated using 0.13um CMOS. The PLLs 8 multiphase clocks can be rotated altogether digitally with respect to a single fixed phase clock from a main PLL. The phase step resolution is 1/15 of a unit bit interval and the rotation is achieved by adding only one additional phase-frequency detector and a charge pump. The rms jitter is 1.2ps for 5Gbps serial link operation. The new PLL occupies 0.015mm2 and consumes 3mA from a 1.2V supply.