Session 23-3

A Split 2-0 MASH with Dual Digital Error Correction

 

Abstract

A dual-path 2-0 cascaded (MASH) ADC was implemented with fast digital correction of both DAC errors and MASH mismatch errors. The split structure allows fast convergence and improved accuracy for the correction. Using a 20 MHz clock, the prototype chip achieved an 84 dB dynamic range in a 1.25 MHz signal band, when fabricated in CMOS 0.18um process.