Session 24-3

A 45nm 2port 8T-SRAM Using Hierarchical Replica
Bitline Technique with Immunity from Simultaneous
R/W Access Issues

 

Abstract

We propose a new 2port SRAM with an 8T single-bit-line memory cell for 45nm SOCs. The Divided read Bit line scheme with Shared local Amplifier realizes fast access time. We also show an important issue of a simultaneous Read and Write access. A rise of the storage node potential causes the misreading. The Read End detecting Replica circuit and the Local read bit line with Dummy Capacitance are introduced to solve it.