Session 25-1

Fast-locking Hybrid PLL Synthesizer Combining
Integer & Fractional Divisions

 

Abstract

This paper reports a single-loop PLL that operates wide-bandwidth fractional-N mode(without any fractional spur reduction circuits) during transient and in a narrow-bandwidth integer-N mode in locked state. This hybrid operation executed via a simple reconfiguration of the single-loop attains both fast locking and design simplicity, a combination that has been previously difficult to achieve. The frequency division mode switching allows the loop bandwidth switching to be performed in a more digital fashion which increases the degree of design freedom for bandwidth switching. A 2.4GHz CMOS prototype synthesizer with a 1MHz resolution performing the hybrid operation has a 20 us lock time for a 64MHz frequency jump, which is 4 times faster than its fixed integer-N operation.