Session 25-3

A 21-GHz Fractional-N Synthesizer in 130-nm CMOS

 

Abstract

A 21-GHz fractional-N PLL was demonstrated in 130-nm CMOS. The PLL consumes 19.6 mW power from a 1.2-V supply. The locking range is from 19 to 21.6 GHz, and the frequency resolution is 10ppm. The measured in-band phase noise at 50-kHz offset and out-of-band phase noise at 20 MHz offset are -67.8 and -121 dBc/Hz.