Session 26-2

An 11 Gb/s 2.4 mW Half-Rate Sampling 2-Tap
DFE Receiver in 65nm CMOS

 

Abstract

A 2-tap DFE receiver, implemented in a 65nm bulk CMOS process, is aggressively optimized for low power and area. The 0.22mW/Gbps power/speed ratio of the receiver and core area of 30um x 40um are achieved by using a half-rate architecture, a sampling front end, soft-decision direct feedback equalization and rail-to-rail CMOS clocking. At 11 Gb/s 2.4mW, the BER is less than 1.0E-14 with a PRBS7 test sequence passing through a 30