Session 26-3

A Jitter-Tolerance-Enhanced CDR Using a GDCOBased
Phase Detector

 

Abstract

A jitter-tolerance-enhanced 10Gb/s clock/data recovery (CDR) is presented. By using a gated-digital-controlled oscillator (GDCO), the proposed GDCO-based phase detector achieves a wide linear range and its jitter tolerance is enhanced without sacrificing the jitter transfer. It has been fabricated in 0.13um CMOS technology and consumes 60mW from a 1.5V supply.