Session 5-1

A 5.1GHz 0.34mm² Router for Network-on-Chip Applications

 

Abstract

A five-port two-lane pipelined packet-switched router core with phase-tolerant mesochronous links forms the key communication fabric for an 80-tile network-on-chip (NoC) architecture. The 15FO4 design combines 102GB/s of raw bandwidth with low fall-through latency of 980ps. A shared crossbar architecture with a double-pumped crossbar switch enables a compact 0.34mm2 router layout. In a 65nm eight-metal CMOS process, the router contains 210K transistors and operates at 5.1GHz at 1.2 V, while dissipating 945mW.