Session 7-1

A 1.35 GS/s, 10b, 175 mW Time-Interleaved
AD Converter in 0.13μm CMOS

 

Abstract

A time-interleaved ADC is presented with 16 channels, each consisting of two Successive Approximation (SA) ADCs in a pipeline configuration. Three techniques are presented to increase the speed of an SA-ADC. Single channel performance is 6.9 ENOB at an input frequency of 4 GHz. Multi-channel performance is 7.7 ENOB at 1.35 GS/s with an ERBW of 1 GHz and a FoM of 0.6 pJ/conversion-step. Keywords: ADC, SAR, SA-ADC, time-interleaved, T/H.