Session 8-5

Investigation of Increased Multi-Bit Failure Rate Due to Neutron
Induced SEU in Advanced Embedded SRAMs

 

Abstract

This paper reports a dramatically increased multi-bit failure rate due to neutron induced single event upset (SEU) in 65nm triple-well embedded SRAMs. Based on detailed fail-pattern analysis and circuit simulation a novel failure model is developed and relaxed ECC guidelines are derived.