Session 10A-2

A Cost-Effective LOP/LSTP Integrated CMOS Platform Utilizing Multi-Thickness
SiON Gate Dielectrics with Hafnium for 45-nm Node

 

Abstract

Integration technique enabling Poly/Hf/SiON gate stack with multi-thickness SiON is demonstrated. Two advantages of hafnium dielectric introduction, which enable low cost integration, are discussed; (i) suppression of reverse narrow channel effect and (ii) sharing of ion implantation processes among core logic and I/O transistors. Mobility improvement techniques by surface roughness and local stress reduction, which enable transistor performance boost with no cost addition, are discussed. These techniques realize cost-effective CMOS platform for 45-nm node.