Session 10B-1

Improvement of Performance and Data Retention Characteristics
of Sub-50nm DRAM by HfSiONGate Dielectric

 

Abstract

For the first time, we have successfully integrated HfSiON gate dielectric to DRAM and obtained excellent data retention time. Lower gate leakage current and better mobility of HfSiON than plasma nitrided oxide resulted in a 22% smaller propagation delay measured at CMOS inverter as well as one order of magnitude lower stand-by current for DRAM. Opti-mized gate poly-Si reoxidation and high Vt of HfSiON cell Tr increased DRAM data retention time as much as 2 times longer than plasma nitrided oxide. We demonstrated that HfSiON could enhance performance and be beneficial to date retention time of high thermal budget DRAM at the same time.