Session 11A-2

Integration Friendly Dual Metal Gate TechnologyUsing Dual
Thickness Metal Inserted Poly-SiStacks (DT-MIPS)

 

Abstract

We have successfully developed integration friendly dual metal gate process utilizing a dual thickness metal inserted poly-Si stacks (DT-MIPS) structure; poly-Si/TaN/HfON stacks for nMOS and poly-Si/capping metal layer/AlO/TaN/HfON stacks for pMOS. First, high-selectivity gate etch process can completely remove metal and HfON from the S/D regions with negligible Si recess. Consequently, we can achieve low and symmetrical n/pMOS Vth values of ~ 0.35V. Moreover, excellent drive currents (620/250uA/um for n/pMOS at Ioff=20pA/um and Vdd=1.2V) are obtained.