Session 11A-4

Strain Enhanced FUSI/HfSiON Technology
with Optimized CMOS Process Window

 

Abstract

We report a study on compatibility of performance boosters with FUSI/HfSiON technology, resulting in record high VT NMOS and PMOS devices with 725/370 uA/um (at VDD=1.1V, Ioff=20pA/um and Jg=100/1 mA/cm2). We demonstrate that adding embedded Si0.75Ge0.25 in S/D regions resulted in 45 per cent drive improvement over the FUSI/HfSiON reference, and that the VT distribution is tight. For process simplicity purposes, dual phase Ni FUSI is formed simultaneously in our integration scheme, each phase having its own process window (PW). In this work, we maximized the common CMOS PW by 2 crucial process improvements: shifting up the NMOS FUSI RTP1 temperature PW by nitrogen implantation in NMOS poly gates prior to Ni deposition for FUSI, and extending the PMOS FUSI PW to lower RTP1 temperatures by improved surface preparation after novel poly etch back process.