Session 12A-2

Multiple Stress Memorization In Advanced SOI CMOS Technologies

 

Abstract

Multiple stress memorization in advanced SOI CMOS is enabled by a new stress memorization technique. NMOS drive current increases after low-temperature annealing of a capped amorphized source/drain region, prior to final RTA. Multiple amorphizing implants into the source/drain regions, offset by spacers, further increase NMOS benefits. The benefits of this new technique are fully additive to the benefits from conventional stress memorization techniques at final RTA, and increases NMOS IDSAT by >27%.