Session 12A-4

Highly Efficient Stress Transfer Techniques
inDual Stress Liner CMOS Integration

 

Abstract

Double disposable sidewall spacers (DDSW) process and adhesion reinforcement technique (ART) were proposed to efficiently transfer the liner stress to the FET channel region. A thin sidewall by the DDSW process was designed to compensate decreased channel stress due to pitch scaling and enable channel conductance to improve by +10% for NFETs. For PFETs, a +23% Ion enhancement was achieved by using the ART, avoiding stress degradation of the DSL and optimizing its layout.