Session 2-4

Low V_t Ni-FUSI CMOS Technology Using a DyOCap Layer
with Either Single or Dual Ni-phases

 

Abstract

This paper reports a novel approach to implement low Vt Ni FUSI bulk CMOS by using a Dysprosium Oxide (DyO) cap layer on both HfSiON and SiON host dielectrics. We show for the first time that an ultra-thin DyO cap layer (5A) can lower the NiSi FUSI nFET Vt by 300mV (500mV) on HfSiON (SiON) (resulting in a Vt,lin of 0.25V and 0.18V respectively), without compromising the Tinv (<1A variation), gate leakage, mobility or reliability. We observed that the DyO cap on SiON can convert into a DySiON silicate with similar electrical properties as HfSiON but much lower Vt, greatly improved PBTI and 150x lower Jg wrt SiON. By demonstrating a novel DyO cap layer selective removal process, this work also points out the feasibility to realize low Vt CMOS using either dual phase (NiSi, Ni32Si12) or single phase (Ni2Si) FUSI gate for both n- and pFETs.