Session 3A-2

Impact of Layout, Interconnects and Variability on
CMOS Technology Roadmap

 

Abstract

In this paper, using the new generation of MASTAR software we discuss the CMOS logic roadmap in terms of circuit performance, power dissipation and variability, such as loaded ring oscillator delay as well as through 6T SRAM functionality. It is shown that these criteria will have to be taken into account in addition to the traditional 17% per year delay improvement to construct a new industrially viable roadmap.