Session 3A-4

Layout-Design Methodology of 0.246-μm² -Embedded6T-SRAM
for 45-nm High-Performance System LSIs

 

Abstract

We successfully developed a 0.246-μm2 embedded 6T-SRAM for high performance system LSIs. The 45-nm CMOS platform, which features reversed extension and S/D formation, achieves both high performance logic transistors and SRAM integration. Cell layout is decided by a novel method using SRAM macros, which include over 100 sorts of parametrically designed cell layouts. As a result, the 0.246-μm2 SRAM has been successfully developed with 140 mV of static noise margin at 0.6 V and Vccmin of 0.9 V.