Session 4A-4

Record-High Performance 32 nm Node pMOSFET with Advanced
Two-Step Recessed SiGe-S/D andStress Liner Technology

 

Abstract

Two-step recessed SiGe-S/D pMOSFET has been optimized with a combination of compressed stress liner. Optimization on source and drain overlap, defect control and elevated SiGe-S/D structure are discussed experimentally. As a result of the careful optimization, both of excellent threshold voltage control and high drive current are realized in gate length less than 30 nm. Record high drive current of 714 uA/um at Vdd=1.0V, Ioff =100 nA/um at 24 nm gate length, is demonstrated.