Session 5A-1

Fermi-Level Pinning Position Modulation by Al-Containing Metal
Gate for Cost-Effective Dual-Metal/Dual-High-k CMOS

 

Abstract

We propose cost-effective gate-first dual-metal/dual-high-k CMOS technology in which Fermi-level pinning is positively utilized to reduce Vths for the first time. The systematic investigation shows that the pinning is unavoidable with a thin EOT, but is a stable phenomenon that should be intentionally utilized. In this method, the pinning can be utilized by incorporating sources (Al) to modulate the pinning position from metal gate into high-k. Single-high-k is automatically converted into dual-high-k after the annealing process.