Session 5B-1

0.7 V SRAM Technology with Stress-EnhancedDopant Segregated Schottky (DSS)
Source/DrainTransistors for 32 nm Node

 

Abstract

For the fist time, low supply voltage SRAM operation with stress-enhanced dopant segregated Schottky (DSS) source/drain transistors is demonstrated. At constant SRAM cell current of 40 uA, we achieve two orders of magnitude lower bit-line leakage than conventional technologies at Vdd=0.7 V, while in case of constant bit-line leakage of 10 nA, supply voltage is successfully reduced down by 0.1 V. DSS technology is promising for low voltage SRAM operation for 32 nm node and beyond