Session 8B-1

Band Engineered Charge Trap Layer for highly Reliable
MLC Flash Memory

 

Abstract

A novel multi-level charge trap flash memory with band engineering concept on the trap layer is firstly demonstrated. The engineered band structure, Si3N4/Al2O3/Si3N4 (NAN) was adopted as a trap layer in place of single Si3N4 layer in TANOS structure. Compared to the reference structure of single Si3N4 trap layer, charge trap flash memory based on NAN trap layer shows larger memory window (~10V), which is ideal for multi-level application. In addition, highly reliable operation is also obtained