Session 12-3

A Bandwidth Tracking Technique for a 65nm CMOS Digital Phase-Locked Loop

 

Abstract

This paper presents a technique to achieve the bandwidth-tracking ability of digital PLLs used for clock generation in large digital systems. The technique uses replica delay cells in the DCO and the PD for >100x range of operating frequency. Measurement results show a near constant damping factor and loop bandwidth to reference frequency ratio over 2x of core oscillation frequencies (2.5GHz-5.0GHz) and reference frequencies from 19.5MHz to 312MHz without calibration.