Session 12-5

A 5GHz Phase-Locked Loop Using Dynamic Phase-Error Compensation Technique for Fast Settling in 0.18-um CMOS

 

Abstract

This paper presents a 5GHz phase-locked loop (PLL) with a fast-locking capability. During frequency locking, the proposed fast-settling technique dynamically adjusts the divide ratio of the frequency divider to keep the instantaneous phase error at the PFD input small. As a result, the locking time is greatly reduced. At a loop bandwidth of 20kHz, the measured settling time is about 10us, which is roughly 14x faster than a traditional PLL. Fabricated in a 0.18um CMOS process, this PLL dissipates 9.5mA from a 1.8V supply. The measured phase noise is -117.5dBc/Hz at 1MHz offset.