Session 13-1

A 31ns Random Cycle VCAT-based 4F2 DRAM with Enhanced Cell Efficiency

 

Abstract

This paper reports a functional 4F2 DRAM based on a vertical-channel-access-transistor (VCAT). A new core design methodology is applied to accommodate 4F2 cell array, achieving both high performance and small area. The 88Kb DRAM array is fabricated in a 50Mb test chip at 80nm design rule and the measured random cycle time (tRC) and read latency (tRCD) is 31ns and 8ns, respectively. The core array size is reduced by 29% compared to conventional 6F2 DRAM.