Session 13-2

A Sub-0.9V Logic-compatible Embedded DRAM with Boosted 3T Gain Cell, Regulated Bit-line Write Scheme and PVT-tracking Read Reference Bias

 

Abstract

Circuit techniques for enabling a sub-0.9V logic-compatible embedded DRAM (eDRAM) are presented. A boosted 3T gain cell increases read margin, enhances read speed and improves data retention time. A regulated bit-line write scheme and a read reference bias generator are proposed to cope with write disturbance issues and PVT variations. Measurement results from a 64kb eDRAM test chip implemented in a 65nm low-leakage CMOS process demonstrate the effectiveness of the proposed techniques.