Session 15-1

Session 15-1

A 45nm 24MB On-Die L3 Cache for the 8-Core Multi-threaded Xeon® Processor

Abstract

The 24-way set associative 24MB 8-ported L3 cache for the 8-core Xeon^(R) Processor uses 0.3816 μm² cell in a 45nm high-K dielectric metal gate technology 9-copper layers. It is protected by double-error correction/triple-error detection ECC. The basic building block is designed to support completely different floorplan styles on 2 processors with large L3 cache. Off die fuse storage enables high resolution repair coverage.