Session 15-4

A 45nm 0.6V Cross-Point 8T SRAM with Negative Biased
Read/Write Assist

 

Abstract

We propose a new design solution for embedded SRAM macros with cross point 8T-SRAM for low operating voltage and power. A negative bias technique for VSS and bitline enables us to achieve not only low power and high access speed, but also the large stability for read and write margin. Using 45-nm CMOS technology, we fabricated the SRAM macro based on our proposal and confirmed that the 1Mbit-SRAM successfully operated at 0.6V.