Session 18-1

A Compact 0.8-6GHz Fractional-N PLL with Binary-Weighted D/A Differentiator and Offset-Frequency Delta-Sigma Modulator for Noise and Spurs Cancellation

 

Abstract

A compact, low power and global-mismatch-tolerant 0.8-6GHz fractional-N PLL covers IEEE 802.11abg, PCS/DCS and cellular bands by using a binary-weighted 2nd order digital/analog differentiator (DAD) to achieve 2nd order mismatch shaping and reduce the quantization noise by 25dB, and using a 3rd order offset-frequency delta-sigma modulator to reduce in-band spurs by 20dB in simulation and 8dB in current single-ended practice.