Session 18-2

A 320fs-RMS-Jitter and 300kHz-BW All-Digital Fractional-N PLL with Self-Corrected TDC and Fast Temperature Tacking Loop for WiMax/WLAN 11n

 

Abstract

This paper presents a 3.9-to-5.39GHz all-digital fractional-N PLL for WiMax/WLAN 11n application. The ADPLL uses a self-corrected TDC to achieve meta-stable-error-free operation, wide dynamic range and high timing resolution in a small chip area. The rms jitter from 1kHz to 40MHz is 320fs at 4.51GHz while the calibrated bandwidth is 300kHz. With aid of the fast temperature tracking loop, the operational temperature range is extended to from -40 to 120oC. The loop settling time is 32us.