Session 18-4

A Low-Voltage, 9-GHz, 0.13-um CMOS Frequency Synthesizer With a Fractional Phase-Rotating and Frequency-Doubling Topology

 

Abstract

The paper presents a low-voltage design for a high frequency phase-locked loop (PLL) implemented in standard 0.13-um CMOS technology. The PLL has fractional function through a high-speed phase-rotating operation. In order to provide more high-frequency output, a frequency doubler is employed at the output stage of the voltage-controlled oscillator (VCO). Through the introduction of the transformers, the VCO with the frequency doubler and the divider with the phase-rotating circuit can operate from a 0.5-V supply. The synthesizer provides the tuning range of 8.95 to 9.20 GHz and dissipates below 15 mW. At 9.14-GHz carried frequency with fractional operation, the measured phase noise is -105 dBc/Hz at a 1-MHz offset.