Session 2-4

A Digital Offset-Compensation Scheme for an LA and CDR in 65-nm CMOS

 

Abstract

A digital offset-compensation scheme for a limiting amplifier (LA) and CDR is presented. The proposed scheme detects the LA offset by sampling the CDR recovered clock with the LA output. The scheme eliminates offset-induced data jitter and compensates offset even for levels that saturate the LA output and cause the CDR not to lock. The compensation circuitry consumes 7.2 mW and occupies 160Å~110 É m2, a third the area of the LA.