Session 21-1

A 19Gb/s 38mW 1-Tap Speculative DFE Receiver in 90nm CMOS

 

Abstract

A half-rate sampling 1-tap speculative DFE in 90nm CMOS operates at speeds up to 23Gb/s through ISI cancellation in the input latch of the receiver. The decision threshold of the latch is varied over a wide range without loss of bandwidth or sensitivity. For a 19Gb/s PRBS7 data stream sent over a 10-inch channel (-11dB at 9.5GHz) that results in a closed post-channel input eye, the DFE operates with a BER of 10-8 for 9% UI horizontal eye opening at its output (BER < 10-13 at the eye center), consuming 38mW from a 1V supply.