Session 21-2

A 40Gb/s Decision Feedback Equalizer Using Back-gate Feedback Technique

 

Abstract

A one-tap 40Gb/s decision feedback equalizer (DFE) has been fabricated in 65nm CMOS technology. The proposed DFE adopts an adder by using the back-gate feedback technique to achieve a high operation speed. The measured bit error rate is below 10-11for a 27-1 PRBS of 40Gb/s. The power dissipation is 45mW from 1.2V supply without output buffers.