Session 23-1

A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13um CMOS Process

 

Abstract

This paper reports a 10-bit 50MS/s SAR ADC with a set-and-down capacitor switching method. Compared to the conventional method, the average switching energy is reduced about 81%. At 50MS/s and 1.2V supply, the ADC consumes 0.92mW and achieves an SNDR of 52.8dB, resulting in an FOM of 52fJ/Conversion-step. Fabricated in a 0.13um 1P8M CMOS technology, the ADC only occupies 0.075mm2 active area.