Session 23-2

A 6-bit 50-MS/s Threshold Configuring SAR ADC in 90-nm Digital CMOS

 

Abstract

A threshold configuring SAR ADC is presented that programs comparator thresholds at runtime to approximate the input signal via binary search. Low power and small area are achieved via a dynamic configurable comparator and an asynchronous controller without any feedback DAC. A 6-bit prototype in 90nm CMOS achieves 32dB SNDR at 50MS/s consuming 240uW from 1V analog and 0.7V digital supplies, i.e. 150fJ/conversion-step in only 0.0055mm2 area occupation, a 4x improvement on state-of-the-art designs.