Session 23-3

A 12b 11MS/s Successive Approximation ADC with two comparators in 0.13µm CMOS

 

Abstract

A two-comparator architecture, incorporating deliberate comparator offset and pre-amplifier power management, reduces comparator meta-stability and comparator power consumption in a 12b 11MS/s SAR ADC. A prototype, fabricated in 0.13É m CMOS achieves an FOM, SNDR, SFDR and error rate of 311fJ/conversion step, 62.4dB and 72.8dB and <1.9x~10-12, respectively, at 11MS/s.