Session 23-4

A 1.3uW 0.6V 8.7-ENOB Successive Approximation ADC in a 0.18um CMOS

 

Abstract

A 100KS/s, 1.3uW, 8.7-ENOB successive approximation ADC is proposed with a time-domain comparator which uses a highly digital differential VCDL architecture. Without any reference voltage, the capacitor DAC performs a rail-to-rail conversion range. The ADC, implemented in a standard 0.18um CMOS, shows a FoM of 31fJ/conversion-step with a single supply voltage of 0.6V.