Session 25-1

3D System Integration of Processor and Multi-Stacked SRAMs by Using Inductive-Coupling Links

 

Abstract

This paper describes a three-dimensional (3D) system integration of a fully functional processor chip and two memory chips by using inductive coupling. To attain a shorter link distance for a smaller area and lower power consumption, a new 3D-integrated wire-penetrated multi-layer structure is developed. In addition, to prevent signal degradation due to unused inductors, an "open-skipped-inductor scheme" is proposed. We present the first demonstration that three fabricated chips are successfully AC-coupled by the inductive coupling. The power and area efficiency of the link are 1 pJ/b and 0.15 mm2/Gbps, respectively, which are the same as those of two-chip integration.