Session 25-4

A 1080p@60fps Multi-Standard Video Decoder Chip Designed for Power and Cost Efficiency in a System Perspective

 

Abstract

In this paper, we present a video decoder chip for H.264/AVC high profile, MPEG-1/2 main profile and AVS J-profile, which is capable of 60fps 1080p decoding at 200MHz. By applying a dedicated DRAM sub-system and a 2-D cache architecture, 50% of pins for DRAM connection and 36% of power consumption are saved, compared to state-of-the-art work in a system perspective. Meanwhile, 38% of gate count is reduced by applying resource sharing architectures between the 3 supported video formats.