Session 26-1

A Self-Background Calibrated 6b 2.7GS/s ADC with Cascade-Calibrated Folding-Interpolating Architecture

 

Abstract

We have developed a 6b 2.7GS/s Folding ADC with on-chip self-background calibration in 90nm CMOS. This is the first report of a successful background-calibrated ADC with a sampling rate of multi GHz. The algorithm enabled us to realize a system robust against environmental and process variation. To minimize the power consumption, a cascaded-calibration architecture was developed. The ADC dissipates 50mW at 2.7GS/s from a 1.0V supply. The figure of merit is 0.47pJ/conversion-step, which is the best reported value for multi-GHz ADCs with a resolution of 6bit or more.